1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and in particular, a data error measuring circuit for a semiconductor memory apparatus.
2. Related Art
A conventional semiconductor memory apparatus is designed to store data and to output stored data. Accordingly, a test is needed to determine whether or not the semiconductor memory apparatus can store and output data.
Further, in order to increase reliability of input/output data, if a one-bit error occurs in the data, the semiconductor memory apparatus corrects the one-bit error using the ECC (Error Correction Code) and outputs corrected data. The ECC includes information related to data input to the semiconductor memory apparatus as parity data. The ECC is used to compare the data with the parity data, and when the data to be output has a one-bit error, to correct the data and output corrected data.
As shown in FIG. 1, a conventional data error measuring circuit for a semiconductor memory apparatus includes a data error correction unit 10 having the ECC, and a test result output unit 20.
When an 8-bit first data signal ‘data0<0:7>’ and an 8-bit second data signal ‘data1<0:7>’ are input to the semiconductor memory apparatus, the semiconductor memory apparatus stores the first data signal ‘data0<0:7>’ and a first parity data signal ‘parb_data0<0:3>’ having information about the first data signal ‘data0<0:7>’. The semiconductor memory apparatus further stores the second data signal ‘data1<0:7>’ and second parity data signal ‘parb_data1<0:3>’ that includes information on the second data signal ‘data1<0:7>’.
The data error correction unit 10 receives the first data signal ‘data0<0:7>’, the second data signal ‘data1<0:7>’, the first parity data signal ‘parb_data0<0:3>’, and the second parity data signal ‘parb_data1<0:3>’. The data error correction unit 10 compares the first data signal ‘data0<0:7>’ with the first parity data signal ‘parb_data0<0:3>’ to output a first corrected data signal ‘data_cor0<0:7>’. The data error correction unit 10 compares the second data signal ‘data1<0:7>’ and the second parity data signal ‘parb_data1<0:3>’ to output a second corrected data signal ‘data_cor1<0:7>’. The first and second corrected data signals ‘data_cor0<0:7>’ and ‘data_cor1<0:7>’ are obtained by correcting the first and second data signals ‘data0<0:7>’ and ‘data1<0:7>’ having a one-bit error, respectively.
The test result output unit 20 receives the first corrected data signal ‘data_cor0<0:7>’ and the second corrected data signal ‘data_cor1<0:7>’ to output a test result signal ‘Test_out’, which represents the test result with a logic level.
A general data error measuring circuit for a semiconductor memory apparatus having the above-described configuration is used to write data having the same level to all of the cells and read the data, to detect an error during the test. According to this method, if a one-bit error occurs in the data to be output, the general data error measuring circuit corrects the error and outputs the corrected data.
For example, the first and second data signals ‘data0<0:7>’ and ‘data1<0:7>’ are input at a high level to the semiconductor memory apparatus and then stored therein. The data error correction unit 10 outputs the stored first and second data signals ‘data0<0:7>’ and ‘data1<0:7>’ as the first corrected data signal ‘data_cor0<0:7>’ and the second corrected data signal ‘data_cor1<0:7>’. At this time, even if any one of the bits of the stored first and second data signals ‘data0<0:7>’ and ‘data1<0:7>’ is at a low level, the bits of the first and second corrected data signals ‘data_cor0<0:7>’ and ‘data_cor1<0:7>’ are all at the high level. Accordingly, the test result output unit 20 outputs the test result signal ‘Test_out’ at a high level. If the test result signal ‘Test_out’ is at a high level, then it can be seen that the stored first data signal ‘data0<0:7>’ and the second data signal ‘data1<0:7>’ do not have an error. When the data to be output has a one-bit error, the general data error measuring circuit corrects the error. In respects to a multi-bit error, however, the general data error measuring circuit can only determine whether or not it exists in the data.
Meanwhile, the general semiconductor memory apparatus having the ECC can only detect a multi-bit error, but cannot detect a one-bit error. Accordingly, when any one of the cells, each storing 8-bit data, is defective, the general semiconductor memory apparatus having the ECC cannot detect the defective cell. As a result, reliability of the semiconductor memory apparatus having the ECC may be degraded.